Work closely with the hardware and firmware team to verifiy Graphics pipeline functionality and performance Part of the verification team to identify areas to improve for power and performance for GPU and APU products Understand and analyze the interactions of hardware and firmware, programming models and applications Requirements Expertise in ASIC digital circuit design

Working on Adaptive Clock Generators for CPU and GPU applications, custom mixed signal circuits and logic design in advanced CMOS technologies using custom and semi custom physical design flows Develop and Simulate RTL code in Verilog Design and Simulate Power Management Circuit Architectures on System level, RTL level and on Transistor level using Matlab, SystemVerilog,

Define product features and capabilities, close architecture, and micro architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all feat

The primary responsibility is for server firmware test case development in conjunction with coordination with architects, BIOS developers, vendors, and quality assurance teams to develop robust, innovative server firmware testing for customer reference boards. A successful candidate will employ solid software testing methodologies, debug capabilities, test case reviews an

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD

Creates and enables efficient geographically agnostic processes and tools to optimize quality and consistency of Cadence CAD designs. Proactively explores, pathfinds, and supports state of the art Cadence PCB design and EDA tools and processes to support our internal teams Capable of debugging and solving technical Cadence PCB design and working directly with Cadence for

An in depth knowledge of the following is required Transmission line theory and microwave engineering concepts such as S parameter, impedance, SSN, etc. System level timing analysis considering effects from silicon IO, package, and board. State of the art PCB stack up/construction. In depth knowledge of AC/DC power delivery, power integrity analysis. Expertise in modeling

Lead the design and implementation of SEV SNP live migration for Linux. Identifying bottlenecks and optimizations & features to advantage EPYC CPUs. Drive features and functionality to our partner technical teams including the Linux kernel, virtualization, and security communities. Support the solutions offered by our partner companies. Review code, build unit tests, and

Enable C++ based diagnostics to be run as patterns on Automated Test Equipment (ATE) Run and debug simulations based on these patterns for hardware developed in Verilog Debug waveforms in Verdi Run emulation on FPGA platforms for these patterns Collaborate closely with design and diagnostics teams to understand and adapt C++ diagnostic algorithms for effective ATE testing

Develop an actionable long term strategy for data center management tools and the related APIs for systems that will deploy AMD Instinct GPUs Lead requirements analysis by deeply understanding partner and customer needs for deployment, management and monitoring large GPU enabled clusters at scale Work closely with AMD engineering teams to leverage internal technical insig

Technical leadership and technical direction setting for whole memory PHY RTL team. Working with customers and consumers to understand feature requirements and translate them into implementable specs Definition of RTL architecture, microarchitecture, and design implementation of memory PHYs Documentation of RTL architecture and micro architecture RTL coding, code reviews

Provide comprehensive onsite administrative support for the Data Center GPU & Accelerated Processing team in Santa Clara, accommodating onsite, hybrid, and traveling employees. Interface with executive management, customers, and visitors, redirecting inquiries and issues as needed. Manage departmental financial processes, including budgets, contracts, purchase orders, pay

Isolate generic system level failures into a more focused area of the platform or CPU Drive debug and resolution of Zen CPU validation issues across silicon, firmware/BIOS, and coordinating with memory partners as needed Devise validation strategy from pre silicon through customer adoption working across architecture, silicon design, firmware, validation, and debug teams

Plan and drive large, customer facing programs to deploy servers with AMD GPUs with mega data centers, OEMs, and ODMs. Build and lead program core teams. Report execution status to executives, customers, and co workers. Make critical customer communications. Facilitate closure of complex issues requiring multi party alignment of AMD teams, customers, and partners. Manage

Work with a team of architects to explore new ray tracing technologies in real time and offline applications. Implement new features related to ray tracing. Analyze ray tracing benchmarks and games. Improve ray tracing performance on current and future hardware. Work closely with architects on creating innovative HW/SW solutions. Collaborate with engineers and managers on